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Dr Ajay Kumar Singh

Dr Ajay Kumar Singh

Dr Ajay Kumar Singh
Dr Ajay Kumar Singh is a Professor in Electronics and Communications Engineering at NIIT University (NU). He has 29 years of experience, and his areas of interest are modelling of submicron MOS devices, low power VLSI circuit design, and renewable energy system design.

Prior to joining NU in 2020, Dr Singh worked in Multimedia University Malaysia for 15 years first as Senior Lecturer, and then, as Associate Professor of Engineering and Technology. He began his academic career as a Lecturer in the Department of Electrical and Electronics Engineering in BITS, Pilani in 1995 and was promoted to the post of Assistant Professor in 2003.

Dr Singh has supervised four PhD and seven masters’ theses. He has authored two books and published more than 90 research papers in various international journals and conferences. He has also successfully completed six external projects as either the Principal Investigator or co-investigator. In addition, he is on the editorial team of several research journals and has been part of the technical programme committees at various international conferences.

Qualifications

Experience

Courses taught

Undergraduate (BE/BTech)
Postgraduate courses (Master of Engineering)

Research areas

Consulting areas

Selected publications

Publications

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Journals
  • A.K. Singh, P.Khastgir, O. N. Singh, and  S.P.Ojha, “Local field configuration modes in a weakly guiding fibre with a conically annular core: An analytical study,” Japanese Journal of Applied Physics, Part-2 Letters, vol.32, no.1A/B, 1993, doi: 10.1143/JJAP.32.L71.
  • A.K. Singh, K. H. S. Singh, P. Khastgir, S.P. Ojha, and  O.N. Singh, “Modal cutoff condition of an optical chiral fibre with different chiralities in the core and the cladding,” Journal of Optical Society of America-B, vol. 11, no.7, pp. 1283, Jul. 1994, doi: https://doi.org/10.1364/JOSAB.11.001283.
  • A.  K. Singh, P. Khastgir, and O.N. Singh, “Modal characteristics of EM wave propagation through a chirofibre with different core and cladding admittances,” Optics Communications (Netherlands), vol.115, pp. 256, 1995, doi:10.1016/0030-4018(94)00684-m.
  • A. K. Singh, P. Khastgir, and  O.N. Singh, “Power distribution in a chirofibre filled with distinct core and cladding chiralities,” Optical Fibre Technology,  vol.1, pp. 264, Jun.1995 . [Online]. Available:https://doi.org/10.1006/ofte.1995.1017.
  • A. K. Singh, S. Gurunaraynan, V. Ramachandran, and M. Umashanker, “Edge potential effect on the operation of short–channel devices,” Microelectronics International, , vol.20, no.3, pp. 23-28, 2003 . [Online]. Available:https://doi.org/10.1108/13565360310487918.
  • G. G. Vaidyanaath and A.K. Singh, “An analytical study of substrate current in submicron MOS devices,” European Physical Journal B, vol.42, pp.113-117 2004. [Online]. Available:https://doi.org/10.1140/epjb/e2004-00362-y.
  • A.K. Singh, “Study of avalanche breakdown (MI) mode in submicron MOSFET device,” Microelectronics International, , vol.22, no.1, pp.16-20, 2005. [Online]. Available: https://doi.org/10.1108/13565360510575503.
  • V. P Kiran, R.G. Kumar, A.K. Singh, and S. Gurunarayanan, “A theoretical study of the performance of sub-micron MOSFET devices in the presence of edge potential,” International Journal of Electronics, vol.92, no.5, pp.295-302, 2005 . [Online]. Available: https://doi.org/10.1080/00207210500114083.
  • C. Senthilpari, A.K.Singh and K. Diwakar, “Design of low-power, high performance, 8X8 bit multiplier using a Shannon-based adder cell,” Microelectronics Journal, , vol.39, pp. 812-821, 2008 . [Online]. Available:https://doi.org/10.1016/j.mejo.2007.12.016.
  • K. Diwakar, C. Senthilpari and A.K. Singh, “Highly stable Delta-Sigma Modulator for industrial applications,” IEICE Electronics Express,, vol. 5, no. 15, pp. 530-536, 2008   . [Online]. Available:https://doi.org/10.1587/elex.5.530.
  • C.M.R Prabu and A. K.Singh, “A proposed SRAM cell for low power consumption during write operation,” Microelectronics International,, vol.26, no.1, pp. 37-42, 2009, doi: 10.1108/13565360910923151.
  • C. Senthilpari, K. Diwakar, A.  K. Singh, “Low energy, low latency and high speed array divider circuit using a Shannon theorem based adder,” Recent Patent of Nanotechnology, , vol.3, pp. 61-72, 2009, doi: 10.2174/187221009787003311.
  • K. Diwakar, C. Senthilpari, Lim Way Soong, A. K. Singh “Delta-Sigma modulator based multiplier,” IEICE Electronics Express, vol.6, no.6, pp. 322-328, 2009, doi: 10.1587/elex.6.322.
  • C. Senthilpari, A. K. S and K. Diwakar, “Low power, low latency, high throughput 16-bit CSA adder using non-clocked pass transistor logic,” Journal of Circuits, System and Computers, vol.18, no.3, pp. 581-596, 2009 [Online]. Available:https://doi.org/10.1142/S021812660900527.
  • K. M. Diwakar, C. Senthilpari, A KSingh, L.W.Soong ,“Delta-Sigma modulator based analog multiplier with digital output,” Recent Patents on Electrical Engineering, vol.2, pp. 161-164, 2009, doi: 10.2174/1874476110902020161.
  • K. Diwakar, C. Senthilpari, A. K. Singh, L. W. Soong, “Vector quantized signal dependent Delta-Sigma modulator based high performance three-phase switching converter,” IEICE Electronics Express, vol.6, no.17, pp. 1259-1265, 2009. [Online]. Available:https://doi.org/10.1587/elex.6.1259.
  • TP.Wen and A K. Singh, “A comprehensive analytical study of double-gate MOSFET after considering quantum confinement parameter,” Microelectron. J., vol. 41, no. 2-3, pp. 162-170, 2010, doi: 10.1016/j.mejo.2010.01.014.
  • C.M.R. Prabhu and A. K. Singh “Novel eight-transistor SRAM cell for write power reduction,” IEICE Electronics Express (ELEX), vol.7, no.16, pp. 1175-1181, 2010, doi: 10.1587/elex.7.1175.
  • A. K. Singh “An analytical study of undoped symmetric double gate MOSFET (SDG),” International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, vol. 24, no. 6, pp. 515-525, 2011, doi:10.1002/jnm.796.
  • C.M.R. Prabhu and A. K. Singh “Low-power fast (LPF) SRAM cell for write/read operation,” IEICE Electronics Express, vol. 6, no.18, pp. 1473-1478, 2011, doI:10.1587/elex.8.1473.
  • T. Bhuvaneswar, VPrasad,  A. K. Singh,  and C. Senthilpari, “Performance analysis of reversed binary decision diagram pass transistor logic synthesis,” International Journal of Circuit Theory and Applications, vol.41, no. 8, pp.844-853, Aug. 2013,doi:10.1002/cta.822.
  • A. K. Singh M. M. Seong and C. M. R. Prabhu,  “Low power and high performance single-ended sense amplifier,” Journal of Circuits, Systems, and Computers, vol. 22, no. 7, pp. 1350062-1-1350062-12, 2013, doi:10.1142/S021812661350062X.
  • T.l Bhuvaneswar, V. Prasad, ank  A. K. Singh “Reversed signal propagation BDD based low power pass-transistor logic synthesis,” IEEJ Transactions on Electrical and Electronic Engineering, vol. 8, no. s1, pp. S66 – S71, 2013,doi:10.1002/tee.219..
  • C.M.R Prabhu and  A. K. Singh “Super-fast low power (SFLP) SRAM cell for read/write operation,” International Journal of Computer Applications, vol. 76, no.5, pp. 1-5, 2013, doi: 10.5120/13240-0681.
  • A. K. Singh M. M. Seong,  and C.M.R Prabhu, “A data aware (DA) 9T SRAM cell for low power consumption and improved stability,” International Journal of Circuit Theory and Applications, vol. 42, no. 9, pp. 956-966, Sep.2014,doi:10.1002/cta.1897.
  • C.M.R. Prabhu and A. K. Singh “Low power reliable SRAM cell for write/read operation,” IEICE Electronics Express, vol. 11, no.21, pp. 1-6, 2014, doi: 10.1587/elex.11.20140913.
  • B. Naresh Kumar, A. K. Singh C. M. R. Prabhu, C. Venkataseshaiah, and G. C. Sheng, “Compact analytical model for one dimensional carbon nanotube field effect transistor (CNTFET),” ECS Solid State Letters, vol. 4, no.6, pp. M12-M14, 2015,doi:10.1149/2.0031506ssl.
  • A. K. Singh B. N.  Kumar, and C. M. R. Prabhu, “Study of drain induced barrier lowering (DIBL), threshold voltage roll-off (Vt -roll-off) and drain current in carbon nanotube field-effect transistor (CNTFET),” ECS Journal of Solid State Science and Technology, vol. 4, no.9, pp. M69-M72, 2015, doi:10.1149/2.0231509jss.
  • A. K. Singh M.-S.Saadatzi, C. Venkataseshaiah, “Design of peripheral circuits for the implementation of memory array using data-aware (DA) SRAM cell in 65 nm CMOS technology for low power consumption,” Journal of Low Power Electronics, vol.12, no.1, pp. 9-20, 2016,doi:10.1166/jolpe.2016.1417.
  • A. K. Singh M.S.Saadatzi, and  C. Venkataseshaiah, “Design of a single-ended energy efficient data-dependent-write-assist dynamic (DDWAD) SRAM cell for improved stability and reliability,” Analog Integrated Circuits and Signal Processing, vol.90, no.2, pp. 411-426, 2017, doi:10.1007/s10470-016-0840-z
  • A. K. Singh B. N. Kumar, and G. C. Sheng, “A quantum correction based model for study of quantum confinement effects in nano-scale carbon nanotube field-effect transistor (CNTFET) under inversion condition,” The European Physical Journal Applied Physics (EPJAP), vol. 78, no. 1, pp.1010-P1-1010-P7, 2017,doi:10.1051/epjap/2017170040.
  • G. R. Murthy, A. K. Singh Md. J. Hossen, and  P. Velrajkumar, “Performance analysis of electrical characteristics for short channel effects (SCE) in carbon nano tube field effect transistor (CNTFET) devices,” Journal of Engineering and Applied Sciences, , vol. 12, no. 20, pp. 5116 – 5120, 2017, doi:10.36478/jeasci.2017.5116.5120.
  • G. R. Murthy, A. K. Singh P. Velrajkumar, and T.W.X. Wilson, “Design of low power and high speed comparator using MUX based full adder cell for mobile communications,” American Journal of Applied Sciences, vol.14, no.1, pp. 116-123, 2017, doi: https://doi.org/10.3844/ajassp.2017.116.123.
  • A. K. Singh B. N. Kumar, G. R.Murthy, and C.M.R. Prabu, “A comprehensive analytical study of electrical properties of carbon nanotube field-effect transistor for future nanotechnology,” International Journal of Numerical Modeling: Electronic Networks, Devices and Fields, vol.31, no 1, pp.1-9, 2018, doi: 10.1002/jnm.2261.
  • A. K. Singh “An analytical analysis of quantum capacitance in nano-scale single-wall carbon nano tube field effect transistor (CNTFET),” International Journal of Nanoelectronics and Materials, vol.11, no. 3, pp.249-262, 2018 . [Online]. Available: http://dspace.unimap.edu.my:80/xmlui/handle/123456789/57585
  • S. Subramaniam, A. K.Singh, and G. R. Murthy, “Design of power efficient stable 1-bit full adder circuit,” IEICE Electronics Express, vol.15, no.14, pp. 1-6, 2018,doi:10.1587/elex.15.20180552.
  • L B. Pestanas, G R. Murthy and A. K. Singh, “Application of 32-bit SAR A/D conversion for vibration, impact and shock datalogging,” Journal of Engineering and Applied Sciences, vol. 13, no. 20, pp.8382-8390, 2018, doi:10.36478/jeasci.2018.8382.8390.
  • A. K. Singh “Modeling of electrical behavior of undoped symmetric Double-Gate (DG) MOSFET using carrier-based approach,” COMPEL – The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, vol. 38, no. 2, pp. 815-828, 2019,doi:10.1108/COMPEL-08-2018-0327.
  • P.L. Chong, A. K. Singh S. , and L.Kok,  “Characterization of Aloe Barbadensis Miller leaves as a potential electrical energy source with optimum experimental setup conditions,” PLoS ONE, vol. 14, no. 6, 2019,doi:10.1371/journal.pone.0218758.
  • A. K. Singh T.C. Fui and T. W. X. Wilson, “Threshold voltage model for hetero-gate-dielectric tunneling field effect transistors,” International Journal of Electrical and Computer Engineering (IJECE), vol. 10, no.2, pp.1764-1771, 2020 doi:10.11591/ijece.v10i2.pp1764-1771.
  • A. K.Singh and T. C.Fui, “Dual metal triple-gate-dielectric (DM_TGD) tunnel field effect transistor: A novel structure for future energy efficient device,” Recent Advances in Electrical and Electronic Engineering, vol.14, no. 6, pp.683-693, 2021, doi: 10.2174/2352096514666210715143350.
  • A. K. Singh T. C. Fui, and L.W.Soong, “Drain current model for a hetero-dielectric single gate tunnel field effect transistor (HDSG TFET),” HDSG: Electronic Networks, Devices and Fields,,doi:10.1002/jnm.2980.

Conference papers

  • C. Senthilpari, K. Diwakar, C.M.R. Prabhu, and A. K. Singh “Power deduction in digital signal processing circuit using inventive CPL subtractor circuit,” in 2006 IEEE International Conference on Semiconductor Electronics (ICSE 2006 Proceedings), Nov. 29 – Dec. 1, 2006, pp.820-824, doi: 10.1109/SMELEC.2006.380751.
  • C. Senthilpari, A. K. Singh, and A. Arokiasamy, “Statistical analysis of power delay estimation in adder circuit using non-clocked pass gate families,” in 4th International Conference on Electrical and Computer Engineering (ICECE) 2006, pp.509-513, doi:10.1109/ICECE.2006.355680.
  • C. Senthilpari, K. Diwakar, and A. K. Singh “Low power and high speed 8×8 bit multiplier using non-clocked pass transistor logics,” in International Conference on intelligence and advance systems, (ICIAS) 2007, Nov. 25 -28,2007, pp. 1374-1378. doi: 10.1109/ICIAS.2007.4658609.
  • K. Diwakar, C. Senthilpari and A. K. Singh “Switching converter with highly stable Delta-Sigma modulator,” in ICSE 2008,Nov. 25-272008, pp. 11-17, doi: 10.1109/SMELEC.2008.4770267.
  • K. Diwakar, C. Senthilpari, A. K. Singh and  L.W. Soong, “Analog multiplier with high accuracy,” in International Conference on Computational Intelligence, Communication Systems and Networks (IEEE Computer Society), , Jul. 23-25, 2009 pp. 62-66, doi:10.1109/CICSYN.2009.10.
  • T. Bhuvaneswari, V.C. Prasad, A. K. Singh  and P.W.C. Prasad, “Weights binary decision diagram (WBDD) and its application to matrix multiplication,” in Conference on Innovative Technologies in Intelligent Systems and Industrial Applications (CITISIA 2009), Jul. 25-26, 2009 pp. 470-475, doi: 10.1109/CITISIA.2009.5224162.
  • C.M.R. Prabhu , A. K. Singh T.Hou, and S. Pin, “9T balanced SRAM Cell for low power operation,” in IEEE Symposium on Industrial Electronics and Applications (ISIEA 2009), Oct. 4-6,  2009, pp.68-72, doi: 10.1109/ISIEA.2009.5356504.
  • A. K. Singh C.M.R. Prabhu, T. Hou,and  S. Pin, “A proposed symmetric and balanced 11-T SRAM cell for lower power consumption,” in TENCON 2009 (International technical conference of IEEE), Nov. 23-26, 2009, doi: 10.1109/TENCON.2009.5396237.
  • C. Senthilpari, K.M. Diwakar, and A. K. Singh “High speed and high throughput 8×8 bit multiplier using a Shannon-based adder cell,” in TENCON 2009 (International technical conference of IEEE),  Nov. 23-26,2009, doi: 10.1109/TENCON.2009.5396177.
  • T. Bhuvaneswari, V. C. Prasad, A. K. Singh “Multiple BDD based matrix multiplication,” ICSE2010 Proc. 2010, Jun.28-30, 2010, pp. 130-134, doi: 10.1109/SMELEC.2010.5549400.
  • C.M.R. Prabhu, and  A. K. Singh “A proposed tail transistor based SRAM cell,” 2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010), Oct. 3-5, 2010, pp. 505-508, doi: 10.1109/ISIEA.2010.5679410.
  • C.M.R. Prabhu,  and A. K. Singh “Low-power fast static random access memory cell,” IEEE Conference on Open systems on Computer applications and Industrial Electronics (ICCAIE 2010), Dec. 5-7, 2010, pp. 5-8, doi: 10.1109/ICCAIE.2010.5735036.
  • T. Bhuvaneswari, V.C. Prasad, and  A. K. Singh “Weights binary decision diagrams (WBDD) based  homology detection,” in International Conference on Information Technology, System and Management (ICITSM 2012), Mar. 25-26,, 2012, doi: 10.1109/CITISIA.2009.5224162.
  • T. Bhuvaneswari, L. W. Soong,  A. K. Singh  and V.C. Prasad, “Design of binary decision diagram (BDD) optical adder,” in IEEE International Conference on Advances in Engineering & Technology Research (ICAETR-2014), Aug.1-2, 2014, doi: 10.1109/ICAETR.2014.7012834.
  • B. N. Kumar, A. K. Singh and C.M.R. Prabhu, “A study of drain current in presence of hot carrier effect for sub-micron MOS devices,” in 2014 International Conference on Electrical, Electronics and System Engineering (ICEESE2014), Dec. 9-10, 2014doi: 10.1109/ICEESE.2014.7154571.
  • S. Subramaniam , T.W.X. Wilson , A.K.Singh, and G.R. Murthy, “A proposed reliable and power efficient 14T full adder circuit design,” Proc. of the 2017 IEEE Region 10 Conference, (TENCON), Nov.5-8, 2017, doi: 10.1109/TENCON.2017.8227834.
  • L. B. Pestañas, G. R. Murthy, and  A. Kumar Singh, “ARM based 32bit precision angular degree movement sensing for any rotary shaft mechanism,” in Humanoid, Nanotechnology, Information Technology, Communication and Control, Environment and Management (HNICEM), 2017 IEEE 9th International Conference on, Dec.1-3, 2017, doi: 10.1109/HNICEM.2017.8269478.
  • C. M. R. Prabhu, T. G. Sargunam, A. K. Singh, and M. N. E. Efzan, “Reliable fast SOI SRAM cell for IoT applications,” AIP Conference Proceedings 2045, 2018 ,doi.org/10.1063/1.5080920.
  • T. G.  Sargunam, C.M.R. Prabhu, and A. K. Singh “Design of high performance FinFET SRAM cell for write operation,” in International Conference on Emerging Current Trends in Computing and Expert Technology (COMET 2k19), Mar. 22 -23,2019,  doi: 10.1007/978-3-030-32150-5_91.
  • T. G.  Sargunam , L. W. Soong, C. M. R. Prabhu, and A. K. Singh, “Design and performance analysis of energy efficient 11T SRAM (E2S11T) cell for high performance and low power applications,” in 2021 IEEE International Workshop of Electronics, Control, Measurement, Signals and their Application to Mechatronics (ECMSM), 2021, pp. 1-7, doi: 10.1109/ECMSM51310.2021.9468835.
  • T. G.  Sargunam , L. W. Soong, C. M. R. Prabhu and A. K. Singh, “Design and statistical analysis of low power robust 13T static random access memory cell for IoT applications,” in 2021 IEEE Symposium on Industrial Electronics & Applications (ISIEA), 2021, pp. 1-6, doi: 10.1109/ISIEA51897.2021.9510007.
  • A. K. Singh and N. Kumar, “Renewable and sustainable electrical energy harvested from living plants: An experimental study,” 2021 International Conference on Electrical, Computer, Communications and Mechatronics Engineering (ICECCME), 2021, pp. 01-04, doi:10.1109/ICECCME52200.2021.9590928.

Books and book chapters

  • A. K. Singh “Scaling limits and quantum confinement in nano-scale silicon transistors,” in Quantum Confinement: Effects, Observations and Insights ( Physics Research and Technology series), , R.Parker,  Ed.,2017, ch.  9,,  USA: Nova Publishers  pp. 145-184
  • A. K. Singh “Power efficient date-aware SRAM cell for SRAM-based FPGA architecture,” in Field Programmable Gate Array, G.Dekoulis, Ed., Crotia: InTech Publisher, pp. 22-247. A. K. Singh Long Channel DG MOSFET Modeling: A carrier based approach, Germany: Lambert Academic Publishing, 2019

Awards and recognition

Professional activities and achievements

On the editorial board of:

Other Interests

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